Monthly Archives: November 2018

Intel Chipset and PCH

From: Wikipedia

Traditionally in x86 computers, the processor’s primary connection to the rest of the machine was through the motherboard chipset’s northbridge. The northbridge was directly responsible for communications with high-speed devices (system memory and primary expansion buses, such as PCIe, AGP and PCI cards, being common examples) and conversely any system communication back to the processor. This connection between the processor and northbridge is commonly designated the front side bus (FSB). Requests to resources not directly controlled by the northbridge were offloaded to the southbridge, with the northbridge being an intermediary between the processor and the southbridge. The southbridge handled “everything else”, generally lower-speed peripherals and board functions (the largest being hard disk and storage connectivity) such as USB, parallel and serial communications. The connection between the northbridge and southbridge was normally the PCI bus.[1]

Before 2003, any interaction between a CPU and main memory or an expansion device such as a graphics card(s) — whether AGP, PCI or integrated into the motherboard — was directly controlled by the northbridge IC on behalf of the processor. This made processor performance highly dependent on the system chipset, especially the northbridge’s memory performance and ability to shuttle this information back to the processor. In 2003, however, AMD’s introduction of the Athlon 64-bit series of processors[2] changed this. The Athlon64 marked the introduction of an integrated memory controller being incorporated into the processor itself thus allowing the processor to directly access and handle memory, negating the need for a traditional northbridge to do so. Intel followed suit in 2008 with the release of its Core i series CPUs and the X58 platform.

In newer processors integration has further increased, primarily through the inclusion of the system’s primary PCIe controller and integrated graphics directly on the CPU itself. As fewer functions are left un-handled by the processor, chipset vendors have condensed the remaining northbridge and southbridge functions into a single chip. Intel’s version of this is the “Platform Controller Hub” (PCH), effectively an enhanced southbridge for the remaining peripherals—as traditional northbridge duties, such as memory controller, expansion bus (PCIe) interface and even on-board video controller, are integrated into the CPU die itself (the chipset often contains secondary PCIe connections though). However, the Platform Controller Hub was also integrated into the processor package as a second die for mobile variants of the Skylake processors.

From Wikipedia PCH

Beginning with ultra-low-power Broadwells and continuing with mobile Skylake processors, Intel incorporated the clock, PCI controller, and southbridge IO controllers into the CPU package, eliminating the PCH for a system on a chip (SOC) design. Rather than DMI, these SOCs directly expose PCIe lanes, as well as SATA, USB, and HDA lines from integrated controllers, and SPI/I²C/UART/GPIO lines for sensors. Like PCH-compatible CPUs, they continue to expose DisplayPort, RAM, and SMBus lines. However, a fully integrated voltage regulator will be absent until Cannon Lake.

What is AHCI ?

From:Crucial Forums

AHCI stand for Advance Host Controller Interface. AHCI is a hardware mechanism that allows software to communicate with Serial ATA (SATA) devices (such as host bus adapters) that are designed to offer features not offered by Parallel ATA (PATA) controllers, such as hot-plugging and native command queuing (NCQ). The specification details a system memory structure for computer hardware vendors in order to transfer data between system memory and the device.

Many SATA controllers can enable AHCI either separately or in conjunction with RAID support. Intel recommends choosing RAID mode on their motherboards (which also enables AHCI) rather than the plain AHCI/SATA mode for maximum flexibility, due to the issues caused when the mode is switched once an operating system has already been installed.

AHCI is fully supported out of the box for Microsoft Windows Vista and the Linux operating system from kernel 2.6.19. NetBSD also supports drivers in AHCI mode out of the box in certain versions. Older operating systems require drivers written by the host bus adapter vendor in order to support AHCI.

Advantage of AHCI

  1. Hot-Plugging (will not cover here as it will not affect computer performance)
  2. Native Command Queuing (might improve computer/system/hard disk responsiveness, espcially in multi-tasking environment

Difference between SATA I, SATA II and SATA III

What is the difference between SATA I, SATA II and SATA III?

SATA I (revision 1.x) interface, formally known as SATA 1.5Gb/s, is the first generation SATA interface running at 1.5 Gb/s. The bandwidth throughput, which is supported by the interface, is up to 150MB/s.

SATA II (revision 2.x) interface, formally known as SATA 3Gb/s, is a second generation SATA interface running at 3.0 Gb/s. The bandwidth throughput, which is supported by the interface, is up to 300MB/s.

SATA III (revision 3.x) interface, formally known as SATA 6Gb/s, is a third generation SATA interface running at 6.0Gb/s. The bandwidth throughput, which is supported by the interface, is up to 600MB/s. This interface is backwards compatible with SATA 3 Gb/s interface.

SATA II specifications provide backward compatibility to function on SATA I ports. SATA III specifications provide backward compatibility to function on SATA I and SATA II ports. However, the maximum speed of the drive will be slower due to the lower speed limitations of the port.

Example: SanDisk Extreme SSD, which supports SATA 6Gb/s interface and when connected to SATA 6Gb/s port, can reach up to 550/520MB/s sequential read and sequential write speed rates respectively. However, when the drive is connected to SATA 3 Gb/s port, it can reach up to 285/275MB/s sequential read and sequential write speed rates respectively.