Category Archives: Chipset

Source Code

Cisco 8811 chip : Broadcom Cygnus Soc

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HP EliteBook model spec



SOC No Chip

Intel® Dual Band Wireless-AC 8260



SOC No Chip

Intel® Dual Band Wireless-AC 7265




Intel® Dual Band Wireless-AC 7260




Intel® Centrino® Advanced-N 6205, Dual Band




Intel® Centrino® Advanced-N 6205, Dual Band




Intel® Centrino® Advanced-N 6200, Dual Band

Intel Chipset and PCH

From: Wikipedia

Traditionally in x86 computers, the processor’s primary connection to the rest of the machine was through the motherboard chipset’s northbridge. The northbridge was directly responsible for communications with high-speed devices (system memory and primary expansion buses, such as PCIe, AGP and PCI cards, being common examples) and conversely any system communication back to the processor. This connection between the processor and northbridge is commonly designated the front side bus (FSB). Requests to resources not directly controlled by the northbridge were offloaded to the southbridge, with the northbridge being an intermediary between the processor and the southbridge. The southbridge handled “everything else”, generally lower-speed peripherals and board functions (the largest being hard disk and storage connectivity) such as USB, parallel and serial communications. The connection between the northbridge and southbridge was normally the PCI bus.[1]

Before 2003, any interaction between a CPU and main memory or an expansion device such as a graphics card(s) — whether AGP, PCI or integrated into the motherboard — was directly controlled by the northbridge IC on behalf of the processor. This made processor performance highly dependent on the system chipset, especially the northbridge’s memory performance and ability to shuttle this information back to the processor. In 2003, however, AMD’s introduction of the Athlon 64-bit series of processors[2] changed this. The Athlon64 marked the introduction of an integrated memory controller being incorporated into the processor itself thus allowing the processor to directly access and handle memory, negating the need for a traditional northbridge to do so. Intel followed suit in 2008 with the release of its Core i series CPUs and the X58 platform.

In newer processors integration has further increased, primarily through the inclusion of the system’s primary PCIe controller and integrated graphics directly on the CPU itself. As fewer functions are left un-handled by the processor, chipset vendors have condensed the remaining northbridge and southbridge functions into a single chip. Intel’s version of this is the “Platform Controller Hub” (PCH), effectively an enhanced southbridge for the remaining peripherals—as traditional northbridge duties, such as memory controller, expansion bus (PCIe) interface and even on-board video controller, are integrated into the CPU die itself (the chipset often contains secondary PCIe connections though). However, the Platform Controller Hub was also integrated into the processor package as a second die for mobile variants of the Skylake processors.

From Wikipedia PCH

Beginning with ultra-low-power Broadwells and continuing with mobile Skylake processors, Intel incorporated the clock, PCI controller, and southbridge IO controllers into the CPU package, eliminating the PCH for a system on a chip (SOC) design. Rather than DMI, these SOCs directly expose PCIe lanes, as well as SATA, USB, and HDA lines from integrated controllers, and SPI/I²C/UART/GPIO lines for sensors. Like PCH-compatible CPUs, they continue to expose DisplayPort, RAM, and SMBus lines. However, a fully integrated voltage regulator will be absent until Cannon Lake.